Invention Grant
- Patent Title: Method to analyze an analog circuit design with a verification program
- Patent Title (中): 用验证程序分析模拟电路设计的方法
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Application No.: US11334063Application Date: 2006-01-17
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Publication No.: US07643979B2Publication Date: 2010-01-05
- Inventor: Qiang Hong , Kevin D. Jones , Paul Wong
- Applicant: Qiang Hong , Kevin D. Jones , Paul Wong
- Applicant Address: US CA Los Altos
- Assignee: Rambus Inc.
- Current Assignee: Rambus Inc.
- Current Assignee Address: US CA Los Altos
- Agency: Hickman Palermo Truong & Becker LLP
- Main IPC: G06F17/50
- IPC: G06F17/50 ; G01R31/28

Abstract:
Data structures and algorithms are provided to automatically generate an analog stimulus to apply to a simulation of the analog DUT. A constraint solver is provided to determine suitable values to use in the stimulus generation. The suitable values are random values within a range of allowed values. For example, a number of different stimuli are generated for successive application to the analog DUT, each with a different magnitude within a range of allowed magnitudes. Data structures and algorithms are provided to monitor analog electrical properties at nodes of the analog DUT. Data structures and algorithms are provided to define constraints on the analog electrical properties and determine whether the constraints were violated. Data structures and algorithms are provided to define simulation coverage conditions in the analog domain and determine whether the defined analog domain coverage conditions have been satisfied.
Public/Granted literature
- US20070168172A1 Method to analyze an analog circuit design with a verification program Public/Granted day:2007-07-19
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