Invention Grant
US07643601B2 Timing extraction circuit for use in optical receiver that uses clock of frequency equal to one half of data transmission rate, and duty cycle deviation handling circuit for use in optical transmitter and receiver 失效
用于光接收机的定时提取电路,其使用频率等于数据传输速率的一半的时钟,以及用于光发射机和接收机的占空比偏差处理电路

  • Patent Title: Timing extraction circuit for use in optical receiver that uses clock of frequency equal to one half of data transmission rate, and duty cycle deviation handling circuit for use in optical transmitter and receiver
  • Patent Title (中): 用于光接收机的定时提取电路,其使用频率等于数据传输速率的一半的时钟,以及用于光发射机和接收机的占空比偏差处理电路
  • Application No.: US10642519
    Application Date: 2003-08-18
  • Publication No.: US07643601B2
    Publication Date: 2010-01-05
  • Inventor: Naoki KuwataTakuji Yamamoto
  • Applicant: Naoki KuwataTakuji Yamamoto
  • Applicant Address: JP Kawasaki
  • Assignee: Fujitsu Limited
  • Current Assignee: Fujitsu Limited
  • Current Assignee Address: JP Kawasaki
  • Agency: Staas & Halsey LLP
  • Main IPC: H03D3/24
  • IPC: H03D3/24
Timing extraction circuit for use in optical receiver that uses clock of frequency equal to one half of data transmission rate, and duty cycle deviation handling circuit for use in optical transmitter and receiver
Abstract:
The invention concerns an optical transmitter and receiver, and provides an improved timing extraction circuit for use in an optical receiver that uses a clock of a frequency equal to one half the data transmission rate, and a duty cycle deviation handling circuit for use in the optical transmitter and receiver. The timing extraction circuit uses a PLL circuit containing a phase comparator circuit for performing a phase comparison between a data signal of bit rate B (bits/s) and a clock signal of B/2 (Hz) at intervals of 2/B (sec), and comprises: a detection circuit for detecting the absence of an output of phase comparison information from the phase comparator circuit by receiving a data signal of a prescribed pattern; and a control circuit for controlling, upon detecting the absence, the phase of the clock signal in order to maintain synchronization. Based on the result of evaluating the duty cycle between the input data before and after the point at which the PLL circuit is locked, the duty cycle deviation handling circuit controls the data discrimination phase before and after that point.
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