A semiconductor memory device includes a memory cell array having a plurality of memory cells, a redundancy cell array having a plurality of redundancy cells, and a detection circuit which detects a bad bit line at an end of a bad column of the memory cell array. The semiconductor memory device further includes a repair circuit which repairs the bad column of the memory cell array by use of the redundancy cell array and repairs an adjacent column which lies adjacent to the bad column on the bad bit line side detected by the detection circuit by use of the redundancy cell array.