Invention Grant
- Patent Title: Non volatile semiconductor memory device
- Patent Title (中): 非易失性半导体存储器件
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Application No.: US11756936Application Date: 2007-06-01
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Publication No.: US07643358B2Publication Date: 2010-01-05
- Inventor: Michio Nakagawa , Hiroshi Nakamura
- Applicant: Michio Nakagawa , Hiroshi Nakamura
- Applicant Address: JP Tokyo
- Assignee: Kabushiki Kaisha Toshiba
- Current Assignee: Kabushiki Kaisha Toshiba
- Current Assignee Address: JP Tokyo
- Agency: Oblon, Spivak, McClelland, Maier & Neustadt, L.L.P.
- Priority: JP2006-155407 20060602
- Main IPC: G11C7/00
- IPC: G11C7/00

Abstract:
A non volatile semiconductor memory device wherein it is possible to transfer Vpp without a drop in voltage of the transfer transistor Vth (threshold voltage) in a transfer circuit or decoder circuit for selectively transferring Vpp by using a usual LVP (low voltage P type transistor) to reduce step(s) of production process and costs. An LVP (low voltage P type transistor) instead of a HVP (high voltage P type transistor) for a transfer circuit is used. Two-way diodes each of which threshold value becomes about Vdd are inserted between the gate and the drain.
Public/Granted literature
- US20070278555A1 NON VOLATILE SEMICONDUCTOR MEMORY DEVICE Public/Granted day:2007-12-06
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