Invention Grant
US07643357B2 System and method for integrating dynamic leakage reduction with write-assisted SRAM architecture
有权
将动态泄漏减少与写辅助SRAM架构相结合的系统和方法
- Patent Title: System and method for integrating dynamic leakage reduction with write-assisted SRAM architecture
- Patent Title (中): 将动态泄漏减少与写辅助SRAM架构相结合的系统和方法
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Application No.: US12032798Application Date: 2008-02-18
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Publication No.: US07643357B2Publication Date: 2010-01-05
- Inventor: George M. Braceras , Steven H. Lamphier , Harold Pilo , Vinod Ramadurai
- Applicant: George M. Braceras , Steven H. Lamphier , Harold Pilo , Vinod Ramadurai
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Cantor Colburn LLP
- Agent Michael LeStrange
- Main IPC: G11C5/14
- IPC: G11C5/14 ; G11C11/00

Abstract:
A system for integrating dynamic leakage reduction with a write-assisted SRAM architecture includes power line selection circuitry associated with each column of one or more SRAM sub arrays, controlled by a selection signal that selects the associated sub array for a read or write operation, and by a column write signal that selects one of the columns of the sub arrays. The power line selection circuitry locally converts a first voltage, corresponding to a cell supply voltage for a read operation, to a second lower voltage to be supplied to each cell selected for a write operation, as to facilitate a write function. The power line selection circuitry also locally converts the first voltage to a third voltage to be supplied to power lines in unselected sub arrays, the third voltage also being lower than the first voltage so as to facilitate dynamic leakage reduction.
Public/Granted literature
- US20090207650A1 SYSTEM AND METHOD FOR INTEGRATING DYNAMIC LEAKAGE REDUCTION WITH WRITE-ASSISTED SRAM ARCHITECTURE Public/Granted day:2009-08-20
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