An electrically erasable programmable read-only memory (EEPROM) device of the NAND type having sideface electrodes as auxiliary electrodes on the opposite lateral surfaces of a transistor channel region to thereby improve operation margins is discusssed. The NAND EEPROM, also known as NAND flash memory, has on a semiconductive substrate an array of memory cells including a serial combination of memory cell transistors. Each of memory cell transistors has a pair of source and drain regions, a channel region, a tunnel insulator film, a charge storage layer, a control dielectric film, a control electrode, a sideface dielectric film on the sidefaces of the channel region, and sideface electrodes which are formed on the side surfaces of channel region with the channel region being laterally interposed therebetween. The sideface electrodes are commonized or “shared” by adjacent ones of the serially coupled memory cell transistors.