A semiconductor memory device comprises a one-transistor (1-T) field effect transistor (FET) type ferroelectric device connected between a pair of bit lines and controlled by a word line, where a different channel resistance is induced to a channel region depending on a polarity state of a ferroelectric layer; a plurality of access transistors connected between the ferroelectric device and the pair of bit lines; and a plurality of port word lines configured to select the plurality of access transistors.