Invention Grant
US07642863B2 Systems and methods for PLL linearity measurement, PLL output duty cycle measurement and duty cycle correction
失效
PLL线性度测量,PLL输出占空比测量和占空比校正的系统和方法
- Patent Title: Systems and methods for PLL linearity measurement, PLL output duty cycle measurement and duty cycle correction
- Patent Title (中): PLL线性度测量,PLL输出占空比测量和占空比校正的系统和方法
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Application No.: US11952706Application Date: 2007-12-07
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Publication No.: US07642863B2Publication Date: 2010-01-05
- Inventor: Masaaki Kaneko , David W. Boerstler , Eskinder Hailu , Jieming Qi
- Applicant: Masaaki Kaneko , David W. Boerstler , Eskinder Hailu , Jieming Qi
- Applicant Address: JP Tokyo US NY Armonk
- Assignee: Kabushiki Kaisha Toshiba,International Business Machines Corporation
- Current Assignee: Kabushiki Kaisha Toshiba,International Business Machines Corporation
- Current Assignee Address: JP Tokyo US NY Armonk
- Agency: Law Offices of Mark L. Berrier
- Main IPC: G01R23/00
- IPC: G01R23/00 ; H03L7/06

Abstract:
Systems and methods for enabling the determination of voltage controlled oscillator (VCO) linearity, duty cycle determination and duty cycle correction in phase locked loop circuits (PLL's.) One embodiment comprises a method including the steps of determining the frequency response of a PLL's VCO as a function of duty cycle, applying a signal based on the VCO output to the VCO input, measuring the resulting frequency of the VCO output signal, determining the duty cycle corresponding to the measured frequency, and configuring a duty cycle correction unit correct the duty cycle of the VCO output signal to about 50%. Determining the frequency response of the VCO may include, for each of several different duty cycle values between 0% and 100%, applying the VCO input signal to the VCO and determining the corresponding frequency of the VCO output signal. This may also be done for duty cycles of 0% and 100%.
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