Invention Grant
- Patent Title: Digital phase locked loop
- Patent Title (中): 数字锁相环
-
Application No.: US11939894Application Date: 2007-11-14
-
Publication No.: US07642862B2Publication Date: 2010-01-05
- Inventor: Robertus Laurentius van der Valk , Paul Hendricus Lodewijk Maria Schram , Johannes Hermanus Aloysius de Rijk
- Applicant: Robertus Laurentius van der Valk , Paul Hendricus Lodewijk Maria Schram , Johannes Hermanus Aloysius de Rijk
- Applicant Address: CA
- Assignee: Zarlink Semiconductor Inc.
- Current Assignee: Zarlink Semiconductor Inc.
- Current Assignee Address: CA
- Agent Lawrence E. Laubscher, Jr.
- Priority: GB0622948.8 20061117
- Main IPC: H03L7/06
- IPC: H03L7/06

Abstract:
A digital phase locked loop includes a phase acquisition unit for producing a digital representation of the phase of a reference signal, a digital phase detector having a first input receiving a digital signal from, or derived from, the output of the phase acquisition unit, digital loop filter filtering the output of the digital phase detector, and a digital controlled oscillator generating an output signal under the control of the digital loop filter. A digital feedback loop provides a second input to the digital phase detector from the output of the digital controlled oscillator.
Public/Granted literature
- US20080116982A1 DIGITAL PHASE LOCKED LOOP Public/Granted day:2008-05-22
Information query