Invention Grant
US07642836B2 Systems and methods for minimizing static leakage of an integrated circuit
有权
用于最小化集成电路的静态泄漏的系统和方法
- Patent Title: Systems and methods for minimizing static leakage of an integrated circuit
- Patent Title (中): 用于最小化集成电路的静态泄漏的系统和方法
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Application No.: US11998762Application Date: 2007-11-30
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Publication No.: US07642836B2Publication Date: 2010-01-05
- Inventor: Randy J. Caplan , Steven J. Schwake
- Applicant: Randy J. Caplan , Steven J. Schwake
- Applicant Address: CA Ottawa, Ontario
- Assignee: MOSAID Technologies Incorporated
- Current Assignee: MOSAID Technologies Incorporated
- Current Assignee Address: CA Ottawa, Ontario
- Agency: Hamilton, Brook, Smith & Reynolds, P.C.
- Main IPC: G05F1/10
- IPC: G05F1/10
Abstract:
A leakage manager system for adequately minimizing static leakage of an integrated circuit is disclosed. The leakage manager system includes a generator configured to generate a control signal to be applied to a sleep transistor. A monitor is configured to determine whether to adjust the control signal to adequately minimize the static leakage. In some embodiments, the monitor includes an emulated sleep transistor. A regulator is configured to adjust the control signal depending on the determination.
Public/Granted literature
- US20080088358A1 Systems and methods for minimizing static leakage of an integrated circuit Public/Granted day:2008-04-17
Information query
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