Invention Grant
- Patent Title: Multiple-mode compensated buffer circuit
- Patent Title (中): 多模式补偿缓冲电路
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Application No.: US11768496Application Date: 2007-06-26
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Publication No.: US07642807B2Publication Date: 2010-01-05
- Inventor: Dipankar Bhattacharya , Gregg R. Harleman , Makeshwar Kothandaraman , John C. Kriz , Bernard L. Morris
- Applicant: Dipankar Bhattacharya , Gregg R. Harleman , Makeshwar Kothandaraman , John C. Kriz , Bernard L. Morris
- Applicant Address: US PA Allentown
- Assignee: Agere Systems Inc.
- Current Assignee: Agere Systems Inc.
- Current Assignee Address: US PA Allentown
- Agency: Ryan, Mason & Lewis, LLP
- Main IPC: H03K17/16
- IPC: H03K17/16

Abstract:
A compensated buffer circuit operative in one of at least a first mode and a second mode includes a plurality of output blocks and a plurality of predrivers, each of the predrivers having an output connected to an input of a corresponding one of the output blocks. Respective outputs of the output blocks are connected together and form an output of the buffer circuit. The output blocks are arranged in a sequence and are binary weighted such that a drive strength of a given one of the output blocks is about twice as large as a drive strength of an output block immediately preceding the given output block. Each of the predrivers selectively enables the corresponding output block connected thereto as a function of a control signal supplied to the predriver for compensating the buffer circuit for PVT variations to which the buffer circuit may be subjected. The respective control signals supplied to the predrivers collectively represent a binary code word, the binary code word in the second mode being equivalent to an arithmetic shift of the binary code word in the first mode.
Public/Granted literature
- US20090002017A1 Multiple-Mode Compensated Buffer Circuit Public/Granted day:2009-01-01
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