Example embodiments of the present invention include an address pin reduction mode circuit with parallel inputs and a method for testing a semiconductor memory device in an address pin reduction mode based on parallel input-based addressing. A reduction in the number of address pins is achieved by use of a common pin for address pins and data enable/disable pins in the semiconductor memory device. The address pin reduction mode circuit with parallel inputs for a semiconductor memory device is capable of reducing test costs by performing tests in an address pin reduction mode based on parallel input-based addressing, as opposed to serial addressing. Even when the semiconductor memory device has more address pins, example embodiments may include a first switch formed to include two address channels coupled to two channels of the tester. A second switch may be coupled to two data enable/disable pins having respective connections to the two channels of the tester. The first and second switches are structured to select the address and data enable/disable signals from the tester responsive to a mode register set (MRS) code corresponding to a test mode. A third switch may be configured to select a chip enable signal /CE and transmit the chip enable signal /CE to a data enable/disable channel responsive to the MRS code when the second switch is off. An address coding unit may be configured to provide a coded address to the two address channels responsive to the MRS code when the first switch is off.