Invention Grant
US07642800B2 Wafer test system wherein period of high voltage stress test of one chip overlaps period of function test of other chip
有权
晶片测试系统，其中一个芯片的高压应力测试周期与其他芯片的功能测试周期重叠
- Patent Title: Wafer test system wherein period of high voltage stress test of one chip overlaps period of function test of other chip
- Patent Title (中): 晶片测试系统，其中一个芯片的高压应力测试周期与其他芯片的功能测试周期重叠
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Application No.: US11848954Application Date: 2007-08-31
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Publication No.: US07642800B2Publication Date: 2010-01-05
- Inventor: Tzong-Yau Ku , Chien-Ru Chen , Chin-Tien Chang , Ying-Lieh Chen , Lin-Kai Bu
- Applicant: Tzong-Yau Ku , Chien-Ru Chen , Chin-Tien Chang , Ying-Lieh Chen , Lin-Kai Bu
- Applicant Address: TW Tainan County
- Assignee: Himax Technologies Limited
- Current Assignee: Himax Technologies Limited
- Current Assignee Address: TW Tainan County
- Agency: J.C. Patents
- Main IPC: G01R31/02
- IPC: G01R31/02 ; G01R31/26
Abstract:
A wafer, a test system thereof, a test method thereof and a test device thereof are provided. The present invention utilizes a first group of probes to perform a high voltage stress (HVS) test on a first chip, and utilizes a second group of probes to perform a function test on a second chip, where a period of the high voltage stress test overlaps a period of the function test, thereby greatly decreasing the test time of the wafer.
Public/Granted literature
- US20090058438A1 WAFER, TEST SYSTEM THEREOF, TEST METHOD THEREOF AND TEST DEVICE THEREOF Public/Granted day:2009-03-05
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