Invention Grant
US07642654B2 Multilayer wiring structure of semiconductor device, method of producing said multilayer wiring structure and semiconductor to be used for reliability evaluation
有权
半导体装置的多层布线结构，制造所述多层布线结构体的方法和用于可靠性评价的半导体装置
- Patent Title: Multilayer wiring structure of semiconductor device, method of producing said multilayer wiring structure and semiconductor to be used for reliability evaluation
- Patent Title (中): 半导体装置的多层布线结构，制造所述多层布线结构体的方法和用于可靠性评价的半导体装置
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Application No.: US12236914Application Date: 2008-09-24
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Publication No.: US07642654B2Publication Date: 2010-01-05
- Inventor: Shinichi Domae , Hiroshi Masuda , Yoshiaki Kato , Kousaku Yano
- Applicant: Shinichi Domae , Hiroshi Masuda , Yoshiaki Kato , Kousaku Yano
- Applicant Address: JP Osaka
- Assignee: Panasonic Corporation
- Current Assignee: Panasonic Corporation
- Current Assignee Address: JP Osaka
- Agency: McDermott Will & Emery LLP
- Priority: JP9-186140 19970711; JP9-348965 19971218
- Main IPC: H01L23/48
- IPC: H01L23/48 ; H01L23/52 ; H01L29/40
Abstract:
A multilayer wiring structure of a semiconductor device having a stacked structure is arranged to restrain reliability degradation due to stress applied to the region of wiring between opposite upper and lower plugs. The rate of overlap of contact surface between upper plug and wiring on contact surface between lower plug and wiring, is small to the extent that no void is generated. The multilayer wiring structure is produced such that no grain boundary is contained in the region of wiring between upper and lower plugs. The difference in thermal expansion coefficient between the material of wiring and the material of upper and lower plugs, is small to the extent that no void is generated.
Public/Granted literature
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