Invention Grant
- Patent Title: Multi-layer interconnect with isolation layer
- Patent Title (中): 具有隔离层的多层互连
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Application No.: US11560504Application Date: 2006-11-16
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Publication No.: US07642651B2Publication Date: 2010-01-05
- Inventor: Todd Albertson , Darin Miller , Mark Anderson
- Applicant: Todd Albertson , Darin Miller , Mark Anderson
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Knobbe, Martens, Olson & Bear LLP
- Main IPC: H01L23/48
- IPC: H01L23/48 ; H01L23/52 ; H01L29/40
Abstract:
An integrated circuit interconnect is fabricated by using a mask to form a via in an insulating layer for a conductive plug. After the plug is formed in the via, a thin (e.g.,
Public/Granted literature
- US20070069262A1 MULTI-LAYER INTERCONNECT WITH ISOLATION LAYER Public/Granted day:2007-03-29
Information query
IPC分类:
