Invention Grant
- Patent Title: Stacked semiconductor package
- Patent Title (中): 堆叠半导体封装
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Application No.: US11531167Application Date: 2006-09-12
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Publication No.: US07642635B2Publication Date: 2010-01-05
- Inventor: Wataru Kikuchi , Toshio Sugano , Satoshi Isa
- Applicant: Wataru Kikuchi , Toshio Sugano , Satoshi Isa
- Applicant Address: JP Tokyo
- Assignee: Elpida Memory, Inc.
- Current Assignee: Elpida Memory, Inc.
- Current Assignee Address: JP Tokyo
- Agency: Sughrue Mion, PLLC
- Priority: JP2003-53260 20030228; JP2004-50264 20040225
- Main IPC: H01L23/02
- IPC: H01L23/02
Abstract:
A stacked semiconductor package comprises two semiconductor chips (11, 12) each of which has a mounting surface provided with a plurality of chip pins arranged in a predetermined pattern. The semiconductor chips are mounted on opposite surfaces of a substrate (13) so that the mounting surfaces are faced to each other through the substrate. The substrate is provided with a plurality of package pins formed in an area other than a chip mounting area and arranged in a pattern identical to the predetermined pattern. A pair of the corresponding chip pins of the semiconductor chips are connected to a via formed at an intermediate position therebetween by the use of branch wires equal in length to each other. The via is connected by a common wire to the package pin corresponding to the chip pins connected to the via.
Public/Granted literature
- US20070001299A1 STACKED SEMICONDUCTOR PACKAGE Public/Granted day:2007-01-04
Information query
IPC分类:
