A thermal stress resistance evaluating method of a semiconductor device includes: forming a test circuit on a corner of each of unit regions arranged on a wafer in an array arrangement; forming a TEG chip by dicing a TEG chip region which is determined by grouping at least two of the unit regions in a predetermined shape; assembling a packaged TEG chip from the TEG chip; and executing a temperature cycling test on the packaged TEG chip by using the test circuit on the TEG chip. According to such a configuration, by adjusting the predetermined shape, the packaged TEG chip of various sizes can be formed in accordance with the design of the product chip size.