Invention Grant
- Patent Title: MOS devices with reduced recess on substrate surface
- Patent Title (中): 在衬底表面上减少凹槽的MOS器件
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Application No.: US11320012Application Date: 2005-12-27
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Publication No.: US07642607B2Publication Date: 2010-01-05
- Inventor: Chih-Hao Wang , Ta-Wei Wang
- Applicant: Chih-Hao Wang , Ta-Wei Wang
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Slater & Matsil, L.L.P.
- Main IPC: H01L29/78
- IPC: H01L29/78

Abstract:
A MOS device having reduced recesses under a gate spacer and a method for forming the same are provided. The MOS device includes a gate structure overlying the substrate, a sidewall spacer on a sidewall of the gate structure, a recessed region having a recess depth of substantially less than about 30 Å underlying the sidewall spacer, and a silicon alloy region having at least a portion in the substrate and adjacent the recessed region. The silicon alloy region has a thickness of substantially greater than about 30 nm. A shallow recess region is achieved by protecting the substrate when a hard mask on the gate structure is removed. The MOS device is preferably a pMOS device.
Public/Granted literature
- US20070034906A1 MOS devices with reduced recess on substrate surface Public/Granted day:2007-02-15
Information query
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