Invention Grant
- Patent Title: Ferroelectric memory device
- Patent Title (中): 铁电存储器件
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Application No.: US10554541Application Date: 2004-04-26
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Publication No.: US07642583B2Publication Date: 2010-01-05
- Inventor: Hiroshige Hirano
- Applicant: Hiroshige Hirano
- Applicant Address: JP Osaka
- Assignee: Panasonic Corporation
- Current Assignee: Panasonic Corporation
- Current Assignee Address: JP Osaka
- Agency: Wenderoth, Lind & Ponack, L.L.P.
- Priority: JP2003-121194 20030425
- International Application: PCT/JP2004/005991 WO 20040426
- International Announcement: WO2004/097939 WO 20041111
- Main IPC: H01L29/76
- IPC: H01L29/76 ; H01L29/94

Abstract:
A ferroelectric memory device having plural memory cells, each composed of a memory cell transistor and a memory cell capacitor including a lower electrode that is independent for each memory cell capacitor, a ferroelectric layer formed on the lower electrode, and an upper electrode layer formed on the ferroelectric layer. A plurality of the upper electrode layers are connected together and constitute a plate electrode, and the width of the upper electrode is narrower than the width of the ferroelectric layer. Accordingly, by making the width of the upper electrode narrower than the width of the ferroelectric layer, it is possible to prevent current leakage between the upper electrode and the lower electrode, which reduces the placement interval of the memory cell capacitors without causing current leakage between the upper electrode and the lower electrode, and results in a smaller memory cell size.
Public/Granted literature
- US20060208295A1 Ferroelectric memory device Public/Granted day:2006-09-21
Information query
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