Invention Grant
US07642569B2 Transistor structure with minimized parasitics and method of fabricating the same
有权
具有最小化寄生效应的晶体管结构及其制造方法
- Patent Title: Transistor structure with minimized parasitics and method of fabricating the same
- Patent Title (中): 具有最小化寄生效应的晶体管结构及其制造方法
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Application No.: US12366425Application Date: 2009-02-05
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Publication No.: US07642569B2Publication Date: 2010-01-05
- Inventor: David R. Greenberg , Shwu-Jen Jeng
- Applicant: David R. Greenberg , Shwu-Jen Jeng
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Scully, Scott, Murphy & Presser, P.C.
- Agent Todd M. C. Li, Esq.
- Main IPC: H01L29/737
- IPC: H01L29/737
Abstract:
A transistor having minimized parasitics is provided including an emitter having a recessed extrinsic emitter portion atop an intrinsic emitter portion; a base including an intrinsic base portion in electrical contact with the intrinsic emitter portion and an extrinsic base portion in electrical contact with the intrinsic base portion and electrically isolated from the recessed extrinsic emitter portion by a set of emitter/base spacers; and a collector in electrical contact with the intrinsic base portion. The transistor may further include extrinsic base having top surfaces entirely silicided to the emitter/base spacer. Additionally, the transistor may include a base window opening within the transistor's active area. Methods of forming the above-described transistor are also provided.
Public/Granted literature
- US20090134429A1 TRANSISTOR STRUCTURE WITH MINIMIZED PARASITICS AND METHOD OF FABRICATING THE SAME Public/Granted day:2009-05-28
Information query
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