Invention Grant
- Patent Title: Method to improve performance of secondary active components in an esige CMOS technology
- Patent Title (中): 提高二级有源器件性能的方法
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Application No.: US11774820Application Date: 2007-07-09
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Publication No.: US07642197B2Publication Date: 2010-01-05
- Inventor: Periannan Chidambaram , Angelo Pinto
- Applicant: Periannan Chidambaram , Angelo Pinto
- Applicant Address: US TX Dallas
- Assignee: Texas Instruments Incorporated
- Current Assignee: Texas Instruments Incorporated
- Current Assignee Address: US TX Dallas
- Agent Warren L. Franz; Wade J. Brady, III; Frederick J. Telecky, Jr.
- Main IPC: H01L21/302
- IPC: H01L21/302 ; H01L21/461

Abstract:
According to various embodiments, there are eSiGe CMOS devices and methods of making them. The method of making a substrate for a CMOS device can include providing a DSB silicon substrate including a first bonded to a second layer, wherein each layer has a (100) oriented surface and a first direction and a second direction and the first direction of the first layer is approximately aligned with the second direction of the second layer. The method can also include performing amorphization on a selected region of the first layer to form a localized amorphous silicon region and recrystallizing the localized amorphous silicon region across the interface using the second layer as a template, such that the first direction of the first layer in the selected region is approximately aligned with the first direction of the second layer.
Public/Granted literature
- US20090014805A1 METHOD TO IMPROVE PERFORMANCE OF SECONDARY ACTIVE COMPONENTS IN AN ESIGE CMOS TECHNOLOGY Public/Granted day:2009-01-15
Information query
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