Invention Grant
- Patent Title: Three-dimensional package and method of making the same
- Patent Title (中): 三维包装及其制作方法
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Application No.: US11584546Application Date: 2006-10-23
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Publication No.: US07642132B2Publication Date: 2010-01-05
- Inventor: Min-Lung Huang , Wei-Chung Wang , Po-Jen Cheng , Kuo-Chung Yee , Ching-Huei Su , Jian-Wen Lo , Chian-Chi Lin
- Applicant: Min-Lung Huang , Wei-Chung Wang , Po-Jen Cheng , Kuo-Chung Yee , Ching-Huei Su , Jian-Wen Lo , Chian-Chi Lin
- Applicant Address: TW Kaohsiung
- Assignee: Advanced Semiconductor Engineering, Inc.
- Current Assignee: Advanced Semiconductor Engineering, Inc.
- Current Assignee Address: TW Kaohsiung
- Agency: Volentine & Whitt, P.L.L.C.
- Priority: TW95102837A 20060125
- Main IPC: H01L21/44
- IPC: H01L21/44

Abstract:
The present invention relates to a three-dimensional package and a method of making the same. The method comprises: (a) providing a semiconductor body; (b) forming at least one blind hole in the semiconductor body; (c) forming an isolation layer on the side wall of the blind hole; (d) forming a conductive layer on the isolation layer; (e) patterning the conductive layer; (f) removing a part of the lower surface of the semiconductor body and a part of the isolation layer, so as to expose a part of the conductive layer; (g) forming a solder on the lower end of the conductive layer; (h) stacking a plurality of the semiconductor bodies, and performing a reflow process; and (i) cutting the stacked semiconductor bodies, so as to form a plurality of three-dimensional packages. As such, the lower end of the conductive layer and the solder thereon are “inserted” into the space formed by the conductive layer of the lower semiconductor body, so as to enhance the joining between the conductive layer and the solder, and effectively reduce the overall height of the three-dimensional packages after joining.
Public/Granted literature
- US20070172982A1 Three-dimensional package and method of making the same Public/Granted day:2007-07-26
Information query
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