Invention Grant
- Patent Title: Semiconductor wafer dividing method
- Patent Title (中): 半导体晶圆分割方法
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Application No.: US11594196Application Date: 2006-11-08
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Publication No.: US07642113B2Publication Date: 2010-01-05
- Inventor: Tetsuya Kurosawa
- Applicant: Tetsuya Kurosawa
- Applicant Address: JP Tokyo
- Assignee: Kabushiki Kaisha Toshiba
- Current Assignee: Kabushiki Kaisha Toshiba
- Current Assignee Address: JP Tokyo
- Agency: Finnegan, Henderson, Farabow, Garrett & Dunner, L.L.P.
- Priority: JP2005-325022 20051109
- Main IPC: H01L21/00
- IPC: H01L21/00 ; H01L21/46
Abstract:
An element is formed on the major surface of a semiconductor wafer, and a groove is formed in the back surface of the semiconductor wafer along a dicing line or chip dividing line by a mechanical or chemical method. A modified layer is formed by irradiating the groove with a laser, and the semiconductor wafer is divided by using the modified layer as a starting point. The back surface of the semiconductor wafer is removed to at least the depth of the groove.
Public/Granted literature
- US20070105345A1 Semiconductor wafer dividing method Public/Granted day:2007-05-10
Information query
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