Invention Grant
- Patent Title: Method of fabricating semiconductor device
- Patent Title (中): 制造半导体器件的方法
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Application No.: US12213908Application Date: 2008-06-26
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Publication No.: US07642103B2Publication Date: 2010-01-05
- Inventor: Tetsuo Yaegashi
- Applicant: Tetsuo Yaegashi
- Applicant Address: JP Tokyo
- Assignee: Fujitsu Microelectronics Limited
- Current Assignee: Fujitsu Microelectronics Limited
- Current Assignee Address: JP Tokyo
- Agency: Westerman, Hattori, Daniels & Adrian, LLP
- Priority: JP2004-344474 20041129
- Main IPC: H01L21/66
- IPC: H01L21/66

Abstract:
Dicing lines extending longitudinally and transversely, and chip areas surrounded by the dicing lines are formed in a resist mask. Critical-dimension patterns are formed in the dicing lines so as to be paired while placing the center line thereof in between. The dimensional measurement of the resist film having these patterns formed therein is made under a CD-SEM, by specifying a measurement-target chip area out of a plurality of chip areas, and by specifying a position of a critical-dimension pattern on the left thereof. Then, the distance of two linear portions configuring the critical-dimension pattern is measured, wherein a portion at a point of measurement on the measurement-target chip area side as viewed from the center line of the dicing line is measured.
Public/Granted literature
- US20080274568A1 Reticle and method of fabricating semiconductor device Public/Granted day:2008-11-06
Information query
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