The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The method includes providing a substrate including an array area and a peripheral area adjacent to the array area, forming word line structures and source/drain regions in the array area, and a word line protection layer on the array area, forming a first hard mask layer over the substrate and having a step height adjacent to a border between the array area and the peripheral area, forming a bit line contact in the array area and between the word line structures by using the first hard mask layer as a pattern guide, and forming a gate electrode layer on the peripheral area. In some embodiments, the step of forming a word line structures in the array area includes forming a composite word line dielectric including a gate dielectric layer and a barrier liner; forming a lower electrode layer disposed over the composite word line dielectric; forming a graphene layer disposed over the lower electrode layer; and forming an upper electrode layer over the first graphene layer.