Invention Grant
- Patent Title: Transistor structure and processing method therefore
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Application No.: US17394662Application Date: 2021-08-05
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Publication No.: US12159936B2Publication Date: 2024-12-03
- Inventor: Chao-Chun Lu
- Applicant: INVENTION AND COLLABORATION LABORATORY PTE. LTD. , ETRON TECHNOLOGY, INC.
- Applicant Address: SG Singapore; TW Hsinchu
- Assignee: INVENTION AND COLLABORATION LABORATORY PTE. LTD.,ETRON TECHNOLOGY, INC.
- Current Assignee: INVENTION AND COLLABORATION LABORATORY PTE. LTD.,ETRON TECHNOLOGY, INC.
- Current Assignee Address: SG Singapore; TW Hsinchu
- Agency: Birch, Stewart, Kolasch & Birch, LLP
- Main IPC: H01L29/78
- IPC: H01L29/78 ; H01L29/417 ; H01L29/66

Abstract:
A transistor structure includes a semiconductor substrate, a channel layer, a gate structure and a first conductive region. The semiconductor substrate includes a semiconductor surface. The channel layer is independent from the semiconductor substrate and covers the semiconductor surface. The gate structure, covers the channel layer. The first conductive region is coupled to the channel layer.
Public/Granted literature
- US20220320328A1 TRANSISTOR STRUCTURE AND PROCESSING METHOD THEREFORE Public/Granted day:2022-10-06
Information query
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