A layout structure of a capacitive element using a complementary FET (CFET) and having a high breakdown voltage is provided. In the capacitive element, first and second transistors overlap as viewed in plan, and the gates thereof are mutually connected. Third and fourth transistors overlap as viewed in plan, and the gates thereof are mutually connected. Nodes of the first and third transistors are mutually connected through a local interconnect, and nodes of the second and fourth transistors are mutually connected through a local interconnect.