In certain aspects, a memory device includes an array of memory cells and a peripheral circuit. The array of memory cells includes a first memory cell and a second memory cell. The peripheral circuit includes a page buffer circuit and control logic. The page buffer circuit is coupled to the first and second memory cells, respectively, and includes a sense out (SO) node and a cache storage unit. The control logic is coupled to the page buffer and configured to suspend a program operation on the first memory cell responsive to receiving a suspension command indicative of executing a read operation on the second memory cell. The control logic is further configured to control the page buffer circuit to store suspended program information associated with a suspension of the program operation, and initiate the read operation on the second memory cell through the SO node and the cache storage unit.