- Patent Title: Vertical semiconductor device and method for fabricating the same
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Application No.: US18317692Application Date: 2023-05-15
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Publication No.: US12114501B2Publication Date: 2024-10-08
- Inventor: Jin-Ha Kim
- Applicant: SK hynix Inc.
- Applicant Address: KR Icheon
- Assignee: SK hynix Inc.
- Current Assignee: SK hynix Inc.
- Current Assignee Address: KR Icheon
- Priority: KR 20190156872 2019.11.29
- Main IPC: H10B43/27
- IPC: H10B43/27 ; H01L21/28 ; H01L23/522 ; H01L23/532 ; H01L29/08

Abstract:
A method for fabricating a semiconductor device includes: forming a first multi-layer stack including liner layers and a source sacrificial layer over a lower structure; forming a second multi-layer stack including dielectric layers and sacrificial layers over the first multi-layer stack; forming a vertical contact recess extending through the second multi-layer stack and the source sacrificial layer; replacing the source sacrificial layer with a source contact layer; forming a carbon-containing spacer on sidewall of the vertical contact recess; replacing the sacrificial layers with conductive layers; and forming a source contact plug in the vertical contact recess.
Public/Granted literature
- US20230292513A1 VERTICAL SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME Public/Granted day:2023-09-14
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