Invention Grant
- Patent Title: Layout structure and method for fabricating same
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Application No.: US18155759Application Date: 2023-01-18
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Publication No.: US12113531B2Publication Date: 2024-10-08
- Inventor: Yingdong Guo , Jing Xu , Wei Jiang , Xue Shan
- Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.
- Applicant Address: CN Hefei
- Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
- Current Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
- Current Assignee Address: CN Hefei
- Agency: Kilpatrick Townsend & Stockton LLP
- Priority: CN 2210726154.3 2022.06.24
- Main IPC: H03K21/02
- IPC: H03K21/02 ; H05K1/02 ; H04B1/04

Abstract:
A layout structure and a method for fabricating the same. A frequency divider pattern layer includes a first frequency divider region, a second frequency divider region, a third frequency divider region and a fourth frequency divider region arranged centrosymmetrically. A conductor pattern layer includes a first sub-conductor pattern layer and a second sub-conductor pattern layer stacked. The first sub-conductor pattern layer is configured to communicate the first frequency divider region with the second frequency divider region, and communicate the third frequency divider region with the fourth frequency divider region. The second sub-conductor pattern layer is configured to communicate the first frequency divider region with the fourth frequency divider region, and communicate the second frequency divider region with the third frequency divider region. The embodiments reduce a channel transmission difference between different frequency dividers in a frequency divider structure.
Public/Granted literature
- US20230421157A1 LAYOUT STRUCTURE AND METHOD FOR FABRICATING SAME Public/Granted day:2023-12-28
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