Invention Grant
- Patent Title: Minimizing total harmonic distortion and power supply induced intermodulation distortion in a single-ended class-D pulse width modulation amplifier
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Application No.: US17940332Application Date: 2022-09-08
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Publication No.: US12113488B2Publication Date: 2024-10-08
- Inventor: Chandra Prakash , Cory J. Peterson , Eric Kimball
- Applicant: Cirrus Logic International Semiconductor Ltd.
- Applicant Address: GB Edinburgh
- Assignee: Cirrus Logic Inc.
- Current Assignee: Cirrus Logic Inc.
- Current Assignee Address: US TX Austin
- Agency: Jackson Walker L.L.P.
- Main IPC: H03F1/32
- IPC: H03F1/32 ; H03F3/217

Abstract:
An amplifier system may include a first stage having a plurality of inputs configured to receive a differential pulse-width modulation input signal and generate an intermediate signal based on the differential pulse-width modulation input signal, a quantizer configured to generate a modulated signal based on the intermediate signal, a single-ended class-D output stage configured to generate a single-ended output signal as a function of the differential pulse-width modulation input signal, a feedback network configured to feed back the single-ended output signal to a first input of the plurality of inputs and to feed back a ground voltage to a second input of the plurality of inputs, a plurality of buffers, each particular buffer configured to receive a respective component of the differential pulse-width modulation input signal and generate a respective buffered component, and an input network coupled between the plurality of buffers and the first stage. Each particular buffer of the plurality of buffers may include a buffering subcircuit configured to buffer the respective component of the differential pulse-width modulation input signal associated with the particular buffer in order to generate the respective buffered component and a biasing subcircuit configured to limit a magnitude of the respective component of the differential pulse-width modulation input signal driven to circuitry of the buffering subcircuit for driving the respective buffered component.
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