Invention Grant
- Patent Title: Low capacitance through substrate via structures
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Application No.: US17839222Application Date: 2022-06-13
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Publication No.: US12112995B2Publication Date: 2024-10-08
- Inventor: Deepak C. Pandey , Haitao Liu , Chandra Mouli
- Applicant: MICRON TECHNOLOGY, INC.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Dorsey & Whitney LLP
- The original application number of the division: US15062675 2016.03.07
- Main IPC: H01L23/48
- IPC: H01L23/48 ; H01L21/768 ; H01L23/538 ; H01L23/532

Abstract:
Apparatuses and methods are disclosed herein for the formation of low capacitance through substrate via structures. An example apparatus includes an opening formed in a substrate, wherein the opening has at least one sidewall, a first dielectric at least formed on the sidewall of the opening, a first conductor at least formed on the first dielectric, a second dielectric at least formed on the first conductor, and a second conductor at least formed on a sidewall of the second dielectric.
Public/Granted literature
- US20220310486A1 LOW CAPACITANCE THROUGH SUBSTRATE VIA STRUCTURES Public/Granted day:2022-09-29
Information query
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