Invention Grant
- Patent Title: Formation method of chip package with fan-out structure
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Application No.: US17328925Application Date: 2021-05-24
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Publication No.: US12080653B2Publication Date: 2024-09-03
- Inventor: Shing-Chao Chen , Chih-Wei Lin , Tsung-Hsien Chiang , Ming-Da Cheng , Ching-Hua Hsieh
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Current Assignee Address: TW Hsinchu
- Agency: McClure, Qualey & Rodack, LLP
- The original application number of the division: US15292762 2016.10.13
- Main IPC: H01L23/538
- IPC: H01L23/538 ; H01L21/48 ; H01L21/56 ; H01L21/683 ; H01L23/00 ; H01L25/065 ; H01L23/31 ; H01L23/498 ; H01L25/00 ; H01L25/10

Abstract:
A method for forming a chip package is provided. The method includes disposing a semiconductor die over a carrier substrate and forming a protection layer over the carrier substrate to surround the semiconductor die. The method also includes forming a dielectric layer over the protection layer and the semiconductor die. The method further includes planarizing a first portion of the dielectric layer and planarizing a second portion of the dielectric layer after the first portion of the dielectric layer is planarized. In addition, the method includes forming a conductive layer over the dielectric layer after the first portion and the second portion of the dielectric layer are planarized.
Public/Granted literature
- US20210280520A1 FORMATION METHOD OF CHIP PACKAGE WITH FAN-OUT STRUCTURE Public/Granted day:2021-09-09
Information query
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