Invention Grant
- Patent Title: 3D NAND—high aspect ratio strings and channels
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Application No.: US17851943Application Date: 2022-06-28
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Publication No.: US12035529B2Publication Date: 2024-07-09
- Inventor: Rajesh Katkar , Xu Chang , Belgacem Haba
- Applicant: Adeia Semiconductor Inc.
- Applicant Address: US CA San Jose
- Assignee: Adeia Semiconductor Inc.
- Current Assignee: Adeia Semiconductor Inc.
- Current Assignee Address: US CA San Jose
- Agency: Haley Guiliano LLP
- Main IPC: H10B43/27
- IPC: H10B43/27 ; H10B41/27 ; H10B41/35 ; H10B43/35

Abstract:
Aspects of the disclosure relate to forming a completed stack of layers. Forming the completed stack of layers may include forming a first stack of layers on a first substrate and forming a second stack of layers on a second substrate. The first stack of layers may be bonded to the second stack of layers. The first or second substrate may be removed. Prior to bonding the first stack of layers and the second stack of layer, one or more holes may be etched in the first stack of layers. After removing the second substrate, one or more holes may be etched in the second stack of layers, wherein each of the one or more holes in the second stack of layers extend into a corresponding hole in the one or more holes in the first stack of layers.
Public/Granted literature
- US20220328521A1 3D NAND - HIGH ASPECT RATIO STRINGS AND CHANNELS Public/Granted day:2022-10-13
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