Invention Grant
- Patent Title: Nanowire transistor with source and drain induced by electrical contacts with negative Schottky barrier height
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Application No.: US17931052Application Date: 2022-09-09
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Publication No.: US12034078B2Publication Date: 2024-07-09
- Inventor: Paul A. Clifton , Andreas Goebel , Walter A. Harrison
- Applicant: Acorn Semi, LLC
- Applicant Address: US CA Palo Alto
- Assignee: Acorn Semi, LLC
- Current Assignee: Acorn Semi, LLC
- Current Assignee Address: US CA Palo Alto
- Agency: Ascenda Law Group, PC
- The original application number of the division: US15816231 2017.11.17
- Main IPC: H01L29/00
- IPC: H01L29/00 ; B82Y10/00 ; H01L29/06 ; H01L29/08 ; H01L29/417 ; H01L29/423 ; H01L29/775 ; H01L29/78 ; H01L29/786
Abstract:
A nanowire transistor includes undoped source and drain regions electrically coupled with a channel region. A source stack that is electrically isolated from a gate conductor includes an interfacial layer and a source conductor, and is coaxially wrapped completely around the source region, extending along at least a portion of the source region. A Schottky barrier between the source conductor and the source region is a negative Schottky barrier and a concentration of free charge carriers is induced in the semiconductor source region.
Public/Granted literature
Information query
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