Invention Grant
- Patent Title: Package structure including stacked pillar portions
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Application No.: US18311864Application Date: 2023-05-03
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Publication No.: US12033968B2Publication Date: 2024-07-09
- Inventor: Jung-Hua Chang , Szu-Wei Lu , Ying-Ching Shih
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: JCIPRNET
- Main IPC: H01L21/56
- IPC: H01L21/56 ; H01L23/00 ; H01L23/31 ; H01L23/498 ; H01L25/065
Abstract:
A semiconductor structure including an integrated circuit die and conductive bumps is provided. The integrated circuit die includes bump pads. The conductive bumps are disposed on the bump pads. Each of the conductive bumps includes a first pillar portion disposed on one of the bump pads and a second pillar portion disposed on the first pillar portion. The second pillar portion is electrically connected to one of the bump pads through the first pillar portion, wherein a first width of the first pillar portion is greater than a second width of the second pillar portion. A package structure including the above-mentioned semiconductor structure is also provided.
Public/Granted literature
- US20230275055A1 PACKAGE STRUCTURE INCLUDING STACKED PILLAR PORTIONS AND METHOD FOR FABRICATING THE SAME Public/Granted day:2023-08-31
Information query
IPC分类:
