- Patent Title: Interconnect architecture for three-dimensional processing systems
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Application No.: US17224603Application Date: 2021-04-07
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Publication No.: US12033714B2Publication Date: 2024-07-09
- Inventor: Nuwan S. Jayasena , Yasuko Eckert
- Applicant: ADVANCED MICRO DEVICES, INC.
- Applicant Address: US CA Santa Clara
- Assignee: Advanced Micro Devices, Inc.
- Current Assignee: Advanced Micro Devices, Inc.
- Current Assignee Address: US CA Santa Clara
- Main IPC: G11C5/02
- IPC: G11C5/02 ; G06F12/0811 ; G06F12/0815 ; G06F12/0888

Abstract:
A processing system includes a plurality of processor cores formed in a first layer of an integrated circuit device and a plurality of partitions of memory formed in one or more second layers of the integrated circuit device. The one or more second layers are deployed in a stacked configuration with the first layer. Each of the partitions is associated with a subset of the processor cores that have overlapping footprints with the partitions. The processing system also includes first memory paths between the processor cores and their corresponding subsets of partitions. The processing system further includes second memory paths between the processor cores and the partitions.
Public/Granted literature
- US20210312952A1 INTERCONNECT ARCHITECTURE FOR THREE-DIMENSIONAL PROCESSING SYSTEMS Public/Granted day:2021-10-07
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