A display device can include a timing controller; a level shifter including a signal input circuit to receive a first clock signal and a second clock signal, a driving mode conversion circuit to self-generate one or more mode signals based on the first and second clock signals for adjusting a driving mode, and a signal output circuit to generate a plurality of scan clock signals based on the one or more mode signals, the first and second clock signals; a shift register configured to generate a scan signal based on the plurality of scan clock signals; and a display panel configured to display an image based on the scan signal. Also, the level shifter is configured to in response to a width of a pulse of the first clock signal being greater than a threshold value, sequentially output a pulse for each of the plurality of scan clock signals.