Invention Grant
- Patent Title: Method for forming semiconductor structure
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Application No.: US17815253Application Date: 2022-07-27
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Publication No.: US12027601B2Publication Date: 2024-07-02
- Inventor: Yen-Chieh Huang , Hai-Ching Chen , Yu-Ming Lin , Chung-Te Lin
- Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
- Current Assignee Address: TW Hsinchu
- Agency: WPAT LAW
- Agent Anthony King
- The original application number of the division: US17238925 2021.04.23
- Main IPC: H01L29/51
- IPC: H01L29/51 ; H01L21/28 ; H01L29/78

Abstract:
A method for forming a semiconductor structure is provided. The method includes following operations. A layer stack is formed over the substrate. The formation of the layer stack includes the following sub-operations: a blocking layer is formed over the substrate, a lower conductive layer is formed over the blocking layer, a first seed layer is formed over the lower conductive layer, a ferroelectric layer is formed over the first seed layer, and an upper conductive layer is formed over the ferroelectric layer. The layer stack is patterned to form a gate stack over the substrate. A spacer layer is formed over sidewalls of the gate stack. A pattered interlayer dielectric layer is formed over the substrate and the gate stack. A source region and a drain region are formed in the substrate through the patterned interlayer dielectric layer.
Public/Granted literature
- US20220367665A1 METHOD FOR FORMING SEMICONDUCTOR STRUCTURE Public/Granted day:2022-11-17
Information query
IPC分类: