Invention Grant
- Patent Title: Forming isolation regions for separating fins and gate stacks
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Application No.: US17813850Application Date: 2022-07-20
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Publication No.: US12027423B2Publication Date: 2024-07-02
- Inventor: Chung-Ting Ko , Tai-Chun Huang , Jr-Hung Li , Tze-Liang Lee , Chi On Chui
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee Address: TW Hsinchu
- Agency: Slater Matsil, LLP
- The original application number of the division: US16933386 2020.07.20
- Main IPC: H01L21/8234
- IPC: H01L21/8234 ; H01L27/088 ; H01L29/66

Abstract:
A method includes forming a semiconductor fin protruding higher than top surfaces of isolation regions. The isolation regions extend into a semiconductor substrate. A portion of the semiconductor fin is etched to form a trench, which extends lower than bottom surfaces of the isolation regions, and extends into the semiconductor substrate. The method further includes filling the trench with a first dielectric material to form a first fin isolation region, recessing the first fin isolation region to form a first recess, and filling the first recess with a second dielectric material. The first dielectric material and the second dielectric material in combination form a second fin isolation region.
Public/Granted literature
- US20220359299A1 Forming Isolation Regions for Separating Fins and Gate Stacks Public/Granted day:2022-11-10
Information query
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