Invention Grant
- Patent Title: BEOL etch stop layer without capacitance penalty
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Application No.: US17476521Application Date: 2021-09-16
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Publication No.: US12027416B2Publication Date: 2024-07-02
- Inventor: Chanro Park , Koichi Motoyama , Kenneth Chun Kuen Cheng , Chih-Chao Yang
- Applicant: International Business Machines Corporation
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agent Gavin Giraud
- Main IPC: H01L21/768
- IPC: H01L21/768 ; H01L23/522
Abstract:
An etch stop layer is located on top of a first dielectric layer. A conductive line is located on top of the etch stop layer. A second dielectric layer is located above the first dielectric layer. The second dialect layer is in contact with the first dielectric layer.
Public/Granted literature
- US20230080438A1 BEOL ETCH STOP LAYER WITHOUT CAPACITANCE PENALTY Public/Granted day:2023-03-16
Information query
IPC分类:
