Invention Grant
- Patent Title: Diode and method of making the same
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Application No.: US17855735Application Date: 2022-06-30
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Publication No.: US12002891B2Publication Date: 2024-06-04
- Inventor: Alex Usenko , Anthony Caruso , Steven Bellinger
- Applicant: Alex Usenko , Anthony Caruso , Steven Bellinger
- Applicant Address: US MO Lake St. Louis
- Assignee: THE CURATORS OF THE UNIVERSITY OF MISSOURI
- Current Assignee: THE CURATORS OF THE UNIVERSITY OF MISSOURI
- Current Assignee Address: US MO Columbia
- Agency: Brannon Sowers & Cracraft PC
- Agent David E. Novak
- Main IPC: H01L29/861
- IPC: H01L29/861 ; H01L29/66

Abstract:
A method of producing a four-layer silicon diode, including selecting a first silicon wafer, wherein said first silicon wafer is CZ-grown B-doped with orientation, a resistivity of less than 0.01 Ohm-cm, and an oxygen content of greater than 10 ppma, and then selecting a second silicon wafer, wherein said second silicon wafer is CZ-grown P-doped with orientation, a resistivity of less than 0.005 Ohm-cm, and an oxygen content of greater than 10 ppma, followed by cleaning the respective first and second silicon wafers. The wafers are then HF treated to yield respective first and second cleaned wafers, the first cleaned wafer is positioned into a first furnace and the second cleaned wafer is positioned into a second furnace, wherein the first and second furnaces are not unitary. Next is annealing the respective first and second cleaned wafers in a reducing atmosphere to yield respective first and second respective out-diffused gradient wafers, followed by bonding together respective first and second heat-treated wafers to yield a mated and/or bonded four-layer substrate having a first heavy doped n-type layer, a second gradient doped n-type layer, a third gradient doped p-type layer, and a fourth heavy doped p-type layer.
Public/Granted literature
- US20230299210A1 DIODE AND METHOD OF MAKING THE SAME Public/Granted day:2023-09-21
Information query
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