Invention Grant
- Patent Title: Semiconductor memory device and structure
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Application No.: US15243941Application Date: 2016-08-22
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Publication No.: US11956952B2Publication Date: 2024-04-09
- Inventor: Zvi Or-Bach , Jin-Woo Han
- Applicant: Monolithic 3D Inc.
- Applicant Address: US CA San Jose
- Assignee: Monolithic 3D Inc.
- Current Assignee: Monolithic 3D Inc.
- Current Assignee Address: US OR Klamath Falls
- Agency: PatentPC
- Agent Bao Tran
- Main IPC: H10B43/20
- IPC: H10B43/20 ; H01L27/102 ; H10B12/00 ; H10B41/20 ; H10B41/50 ; H10B43/50

Abstract:
A device, including: a first structure including first memory cells, the first memory cells including first transistors; and a second structure including second memory cells, the second memory cells including second transistors, where the second transistors overlay the first transistors, and a plurality of memory cells control lines, where the first transistors are self-aligned to the second transistors, where a second transistor channel of the second transistors is aligned to a first transistor channel of the first transistors, the aligned is at an atomic level as would have been resulted from an epitaxial growth process.
Public/Granted literature
- US20170053906A1 SEMICONDUCTOR MEMORY DEVICE AND STRUCTURE Public/Granted day:2017-02-23
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