Invention Grant
- Patent Title: Formation method of chip package with fan-out feature
-
Application No.: US17554552Application Date: 2021-12-17
-
Publication No.: US11948892B2Publication Date: 2024-04-02
- Inventor: Po-Hao Tsai , Meng-Liang Lin , Po-Yao Chuang , Techi Wong , Shin-Puu Jeng
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Current Assignee Address: TW Hsinchu
- Agency: McClure, Qualey & Rodack, LLP
- The original application number of the division: US16446796 2019.06.20
- Main IPC: H01L23/31
- IPC: H01L23/31 ; H01L21/48 ; H01L21/56 ; H01L23/538 ; H01L25/00 ; H01L25/18

Abstract:
A method for forming a package structure is provided. The method includes forming first conductive structures and a first semiconductor die on a same side of a redistribution structure. The method includes forming an interposer substrate over the redistribution structure, wherein the first semiconductor die is between the interposer substrate and the redistribution structure, and edges of the interposer substrate extend beyond edges of the first semiconductor die. The method includes forming a second semiconductor die on the redistribution structure, wherein the first semiconductor die and the second semiconductor die are disposed on opposite sides of the redistribution structure.
Public/Granted literature
- US20220108956A1 FORMATION METHOD OF CHIP PACKAGE WITH FAN-OUT FEATURE Public/Granted day:2022-04-07
Information query
IPC分类: