Invention Grant
- Patent Title: Semiconductor package and manufacturing method thereof
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Application No.: US17219956Application Date: 2021-04-01
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Publication No.: US11948891B2Publication Date: 2024-04-02
- Inventor: Sang Yong Park , Juhyun Nam
- Applicant: NEPES CO., LTD.
- Applicant Address: KR Eumseong-gun
- Assignee: NEPES CO., LTD.
- Current Assignee: NEPES CO., LTD.
- Current Assignee Address: KR Eumseong-gun
- Agency: NORTON ROSE FULBRIGHT US LLP
- Priority: KR 20200040678 2020.04.03 KR 20200084428 2020.07.09 KR 20200167204 2020.12.03 KR 20210034710 2021.03.17 KR 20210039103 2021.03.25
- Main IPC: H01L23/538
- IPC: H01L23/538 ; H01L23/00 ; H01L23/552 ; H01L25/16

Abstract:
A semiconductor package is provided. The semiconductor package can include a first redistributed layer on which a plurality of semiconductor chips and a plurality of passive devices are mounted on one surface, a second redistributed layer electrically connected to the first redistributed layer through a via, an external connection terminal formed on the lower surface of the second redistributed layer, a first mold provided to cover the plurality of semiconductor chips and the plurality of passive devices on the first redistributed layer, and a second mold provided between the first redistributed layer and the second redistributed layer. Each of the first redistributed layer and the second redistributed layer includes a wiring pattern and an insulating layer and is composed of a plurality of layers, and at least one of the plurality of semiconductor chips is disposed between the first redistributed layer and the second redistributed layer.
Public/Granted literature
- US20210313274A1 SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF Public/Granted day:2021-10-07
Information query
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