PWM-frame rate misalignment is mitigated through implementation of a discrete variable refresh rate (VRR) scheme. A target frame rate is limited to a frame rate selected from only those frame rates that facilitate alignment of each frame period to a specified edge of a PWM cycle of a brightness control signal of a display panel. This alignment results in each frame period at the selected frame rate starting at a same point in a corresponding PWM cycle and ending at a same point in a corresponding PWM cycle to help ensure a constant effective duty cycle across each successive frame period, which in turn mitigates perception of flicker that otherwise would arise. Further, the discrete VRR scheme can employ a compensation mode for compensating for the delay in rendering or otherwise obtaining a frame for display so as to maintain a consistent duty cycle in the brightness control signal.