Invention Grant
- Patent Title: Integrated circuit package and method
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Application No.: US18297927Application Date: 2023-04-10
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Publication No.: US11935804B2Publication Date: 2024-03-19
- Inventor: Tzu-Sung Huang , Ming Hung Tseng , Yen-Liang Lin , Hao-Yi Tsai , Chi-Ming Tsai , Chung-Shi Liu , Chih-Wei Lin , Ming-Che Ho
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: Slater Matsil, LLP
- The original application number of the division: US16427569 2019.05.31
- Main IPC: H01L23/31
- IPC: H01L23/31 ; H01L21/56 ; H01L21/768 ; H01L23/16 ; H01L23/522 ; H01L23/528

Abstract:
In an embodiment, a device includes: an integrated circuit die; an encapsulant at least partially surrounding the integrated circuit die, the encapsulant including fillers having an average diameter; a through via extending through the encapsulant, the through via having a lower portion of a constant width and an upper portion of a continuously decreasing width, a thickness of the upper portion being greater than the average diameter of the fillers; and a redistribution structure including: a dielectric layer on the through via, the encapsulant, and the integrated circuit die; and a metallization pattern having a via portion extending through the dielectric layer and a line portion extending along the dielectric layer, the metallization pattern being electrically coupled to the through via and the integrated circuit die.
Public/Granted literature
- US20230245939A1 Integrated Circuit Package and Method Public/Granted day:2023-08-03
Information query
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