Invention Grant
- Patent Title: Stacked semiconductor device test circuits and methods of use
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Application No.: US17304982Application Date: 2021-06-29
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Publication No.: US11935798B2Publication Date: 2024-03-19
- Inventor: Jen-Yuan Chang
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: Harrity & Harrity, LLP
- Main IPC: H01L21/66
- IPC: H01L21/66 ; H01L23/00 ; H01L23/48 ; H01L25/10

Abstract:
A control circuit is included in a first die of a stacked semiconductor device. The first die further includes a transistor that is electrically connected to the control circuit. The transistor is configured to be controlled by the control circuit to selectively block a die-to-die interconnect. In this way, the die-to-die interconnect may be selectively blocked to isolate the first die and a second die of the stacked semiconductor device for independent testing after bonding. This may increase the effectiveness of a testing to identify and isolate defects in the first die or the second die, which may further increase the effectiveness of performing rework or repair on the stacked semiconductor device.
Public/Granted literature
- US20220344223A1 STACKED SEMICONDUCTOR DEVICE TEST CIRCUITS AND METHODS OF USE Public/Granted day:2022-10-27
Information query
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