A memory device has a memory array of a plurality of memory cells arranged in a plurality of columns and a plurality of rows. The memory cells in each of the plurality of columns include first memory cells and second memory cells alternately arranged along a column direction of the plurality of columns. A first computation circuit is coupled to the first memory cells in each of the plurality of columns, and is configured to generate first output data corresponding to a first computation performed on first weight data stored in the first memory cells. A second computation circuit is coupled to the second memory cells in each of the plurality of columns, and is configured to generate second output data corresponding to a second computation performed on second weight data stored in the second memory cells.