Invention Grant
- Patent Title: Semiconductor device having laterally offset stacked semiconductor dies
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Application No.: US17320116Application Date: 2021-05-13
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Publication No.: US11929349B2Publication Date: 2024-03-12
- Inventor: Chan H. Yoo , Ashok Pachamuthu
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Perkins Coie LLP
- The original application number of the division: US15686029 2017.08.24
- Main IPC: H01L25/065
- IPC: H01L25/065 ; H01L25/00

Abstract:
Semiconductor devices including stacked semiconductor dies and associated systems and methods are disclosed herein. In one embodiment, a semiconductor device includes a first semiconductor die coupled to a package substrate and a second semiconductor die stacked over the first semiconductor die and laterally offset from the first semiconductor die. The second semiconductor die can accordingly include an overhang portion that extends beyond a side of the first semiconductor die and faces the package substrate. In some embodiments, the second semiconductor die includes bond pads at the overhang portion that are electrically coupled to the package substrate via conductive features disposed therebetween. In certain embodiments, the first semiconductor die can include second bond pads electrically coupled to the package substrate via wire bonds.
Public/Granted literature
- US20210272932A1 SEMICONDUCTOR DEVICE HAVING LATERALLY OFFSET STACKED SEMICONDUCTOR DIES Public/Granted day:2021-09-02
Information query
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